M48T08-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48T08-150PC1TR Datasheet - Page 7

• Manufacturer Part Number: M48T08-150PC1TR
• Description: CMOS 8K x 8 TIMEKEEPER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (t
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
A0-A12
E1
E2
G
DQ0-DQ7
AVQV
) after the last address input
tE2HQX
tE1LQX
tAVQV
tE2HQV
tE1LQV
tGLQX
tGLQV
tAVAV
VALID
available after the latter of the Chip Enable Access
times (t
time (t
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before t
an indeterminate state until t
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
Hold time (t
next address access.
GLQV
E1LQV
).
AXQX
VALID
or t
AVQV
) but will go indeterminate until the
E2HQV
M48T08, M48T08Y, M48T18
, the data lines will be driven to
tGHQZ
) or Output Enable Access
AVQV
tAXQX
tE1HQZ
tE2LQZ
. If the address
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