M48T08-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48T08-150PC1TR Datasheet - Page 9

• Manufacturer Part Number: M48T08-150PC1TR
• Description: CMOS 8K x 8 TIMEKEEPER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

WRITE Mode
The M48T08/18/08Y is in the WRITE Mode when-
ever W, E1, and E2 are active. The start of a
WRITE is referenced from the latter occurring fall-
ing edge of W or E1, or the rising edge of E2. A
WRITE is terminated by the earlier rising edge of
W or E1, or the falling edge of E2. The addresses
must be held valid throughout the cycle. E1 or W
must return high or E2 low for a minimum of t
or t
Figure 8. WRITE Enable Controlled, WRITE AC Waveform
E2LAX
from Chip Enable or t
A0-A12
E1
E2
W
DQ0-DQ7
WHAX
tAVE1L
tAVE2H
tAVWL
from WRITE
tWLQZ
E1HAX
tAVWH
tWLWH
tAVAV
VALID
Enable prior to the initiation of another READ or
WRITE Cycle. Data-in must be valid t
the end of WRITE and remain valid for t
terward. G should be kept high during WRITE Cy-
cles to avoid bus contention; however, if the output
bus has been activated by a low on E1 and G and
a high on E2, a low on W will disable the outputs
t
WLQZ
tDVWH
after W falls.
DATA INPUT
tWHDX
M48T08, M48T08Y, M48T18
tWHQX
tWHAX
AI00963
DVWH
WHDX
prior to
9/27
af-