ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet
ADC1443D125HD
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ADC1443D125HD Summary of contents
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ADC1443D series Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs Rev. 03 — 19 July 2012 1. General description The ADC1443D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with JESD204B interface (backward compatible JESD204A) optimized ...
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... Table 1. Ordering information Type number f (Msps) s ADC1443D200HD 200 ADC1443D160HD 160 ADC1443D125HD 125 ADC1443D_SER Objective data sheet Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Package Name Description HLQFN56 plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 8 1.35 mm HLQFN56 plastic thermal enhanced low profile quad flat package ...
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Integrated Device Technology 5. Block diagram Fig 1. Block diagram ADC1443D_SER Objective data sheet Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 03 — 19 July 2012 ADC1443D series © IDT 2012. All rights reserved. 3 ...
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Integrated Device Technology 6. Pinning information 6.1 Pinning Fig 2. Pin configuration (SOT935-2) ADC1443D_SER Objective data sheet Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 03 — 19 July 2012 ADC1443D series © IDT 2012. All ...
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Integrated Device Technology 6.2 Pin description Table 2. Symbol INAM INAP VCMA DNC DNC AGND CLKP CLKN AGND DNC DNC VCMB INBP INBM VDDA VDDA SCLK SDIO SCS_N AGND DNC SCR_EN CFG0/OTRA CFG1/OTRB CFG2 CFG3 VDDO OGND OGND OGND VDDO ...
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Integrated Device Technology Table 2. Symbol VDDO OGND OGND SYNCBP SYNCBN AGND VDDO DNC SYSREFP SYSREFN VDDA AGND AGND VDDA DNC SYSREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1443D_SER Objective data sheet Dual ...
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Integrated Device Technology 7. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DDA V DDO stg T amb Thermal characteristics Table 4. ...
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Integrated Device Technology [1] Table 5. Static characteristics Symbol Parameter P total power dissipation tot Clock inputs: pins CLKP and CLKM (AC-coupled; peak-to-peak) V clock input voltage i(clk) C input capacitance I Logic inputs I LOW-level input current IL I ...
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Integrated Device Technology [1] Table 5. Static characteristics Symbol Parameter Accuracy INL integral non-linearity DNL differential non-linearity E offset error offset E gain error G M channel-to-channel gain G(CTC) matching Supply PSRR power supply rejection ratio [1] Typical values measured ...
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Dynamic characteristics 10.1 Dynamic characteristics Table 6. Dynamic characteristics [1] Symbol Parameter second harmonic level 2H third harmonic level 3H SFDR spurious-free dynamic range THD total harmonic distortion Conditions ...
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Table 6. Dynamic characteristics [1] …continued Symbol Parameter IMD3 third-order intermodulation distortion SNR signal-to-noise ratio ENOB effective number of bits Conditions ADC1443D125 (f = 125 Msps) s Min Typ Max f = ...
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Table 6. Dynamic characteristics [1] …continued Symbol Parameter channel crosstalk ct(ch) [1] Typical values measured 1 DDA DDO 1 dBFS; unless ...
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Integrated Device Technology 10.2 Timing 10.2.1 Clock timing Table 7. Symbol Parameter t data latency time lat(data) t wake-up time wake Clock timing f sampling rate s clock frequency f clk clock duty cycle clk t sampling delay time ...
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Integrated Device Technology Fig 4. SYSREF timing 10.2.3 SPI timing Table 9. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk [1] Typical values measured at V the full temperature range T Fig 5. SPI timing ...
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Integrated Device Technology 10.3 Typical dynamic performances 10.3.1 Typical FFT at 122.88 Msps 1-tone FFT: 1 dBFS; f Fig MHz 122.88 Msps s 1-tone FFT: 14 dBFS; f Fig 122.88 ...
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Integrated Device Technology 10.3.2 Typical FFT at 153.6 Msps Fig 10. 1-tone FFT: 1 dBFS MHz 153.6 Msps s Fig 12. 1-tone FFT: 14 dBFS 153.6 Msps s ADC1443D_SER Objective ...
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Integrated Device Technology 10.3.3 Typical SNR performances Fig 14. SNR as a function of sampling frequency: 1 dBFS 170 MHz i Fig 16. SNR as a function of input amplitude 190 MHz 185 Msps; ...
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Integrated Device Technology 10.3.4 Typical SFDR performances Fig 18. SFDR as a function of sampling frequency: 1 dBFS 170 MHz i Fig 20. SFDR as a function of input amplitude I(dif) ADC1443D_SER Objective data ...
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Integrated Device Technology 10.3.5 Typical IMD3 performances Fig 22. IMD3 as a function of sampling frequency: 7 dBFS 168.5 MHz Fig 24. IMD3 as a function of input amplitude: 3 MHz spacing ...
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Integrated Device Technology 11. Application information 11.1 Analog inputs 11.1.1 Input stage The analog input of the ADC1443D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with respect to the common-mode input voltage ...
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Integrated Device Technology Fig 27. Equivalent schematic of the common-mode reference circuit 11.1.4 Programmable full-scale The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) by programming internal reference gain between 0 dB and ...
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Integrated Device Technology Fig 28. Anti-kickback circuit The input frequency determines the component values. Select values that do not affect the input bandwidth. Table 11. Input frequency range (MHz) 11.1.6 Transformer The input frequency determines the configuration of the transformer ...
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Integrated Device Technology The configuration shown in Figure 30 is recommended for high-frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. Fig 30. Dual transformer configuration (high IF) 11.2 Clock input 11.2.1 Drive ...
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Integrated Device Technology a. Differential sine clock input Fig 32. Sine clock input a. Rising edge LVCMOS Fig 33. LVCMOS single-ended clock input Single-ended or differential clock inputs can be selected via bit DIFF_SE of SPI. If single-ended is enabled, ...
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Integrated Device Technology 11.2.2 Equivalent input circuit Figure 34 shows the equivalent circuit of the input clock buffer. The input signal must be AC-coupled and the common-mode voltage of the differential input stage is set via internal 5 k resistors. ...
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Integrated Device Technology Fig 35. JESD204A/JESD204B serial output - DC-coupled Fig 36. JESD204A/JESD204B serial output - AC-coupled 11.3.2 JESD204A/JESD204B serializer 11.3.2.1 Digital JESD204A/JESD204B formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A/JESD204B ...
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Integrated Device Technology M CONVERTERS N bits from bits for control TX transport layer SYNC~ samples stream to lane stream mapping N bits from Cr + M−1 CS bits for control N' = N+CS CF: position ...
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Integrated Device Technology 11.3.3 OuT-of-Range (OTR) An out-of-range signal is provided on pins OTRA and OTRAB. The latency of OTR is 31 clock cycles. The OTR response can be speeded up by enabling fast OTR using SPI local registers (bit ...
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Integrated Device Technology 11.3.5 Test patterns The ADC1443D can be configured to transmit a number of predefined test patterns using the SPI local registers (bits TEST_PAT_SEL[2:0] in Table 14 and Table 28). The selected test pattern is transmitted regardless of ...
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Integrated Device Technology 11.4 Configuration pins (CFG0, CFG1, CFG2, CFG3) The configuration pins are only active as inputs at start-up. The values on those pins are read once to set up the device. Then the pins become outputs (OTRA and ...
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Integrated Device Technology 11.5 Serial Peripheral Interface (SPI) 11.5.1 Register description The ADC1443D serial interface is a synchronous serial communications port, which allows easy interfacing with many commonly used microprocessors. It provides access to the registers controlling the operation of ...
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Integrated Device Technology • Bits A12 to A0 indicate the address of the register being accessed concerns a multiple byte transfer, this address is the first register accessed. An address counter is increased to access subsequent addresses. The ...
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Register allocation map Table 19 shows an overview of all registers. Table 19. Register allocation map Addr. Register R/W (hex) name Bit 7 ADC control registers 0000h CHIP_RST RW 0001h CHIP_ID ...
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Table 19. Register allocation map …continued Addr. Register R/W (hex) name Bit 7 0806h IP_CTRL2 R/W 080Bh IP_PRBS_ R/W CTRL 0816h IP_DEBUG_ R/W - OUT1 0817h IP_DEBUG_ R/W OUT2 0818h IP_DEBUG_ R/W ...
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Table 19. Register allocation map …continued Addr. Register R/W (hex) name Bit 7 0871h LANE00_0_ R/W RESERVED[2:0] CTRL 0872h LANE01_0_ R/W RESERVED[2:0] CTRL 0890h ADC00_0_ R/W - CTRL 0891h ADC01_0_ R/W - ...
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Integrated Device Technology 11.5.3 Detailed register description The tables in this section contain detailed descriptions of the registers. 11.5.3.1 ADC control registers Table 20. CHIP_RESET register (address 0000h) bit description Default settings are shown highlighted. Bit Symbol ...
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Integrated Device Technology Table 23. CLK_CFG register (address 0007h) bit description Default settings are shown highlighted. Bit Symbol CLK_DIV[1:0] Table 24. INTERNAL_REF register (address 0008h) bit description Default settings are shown highlighted. Bit Symbol ...
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Integrated Device Technology Table 26. OUTPUT_CFG register (address 0011h) bit description Default settings are shown highlighted. Bit Symbol [ DATA_FORMAT[1:0:] [1] Local register Table 27. DIG_OFFSET register (address 0013h) bit description Default settings are shown highlighted. Bit ...
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Integrated Device Technology Table 31. OTR_CFG register (address 0017h) bit description Default settings are shown highlighted. Bit Symbol [1] 3 FAST_OTR [ FAST_OTR_DET[2:0] [1] Local register Table 32. TRANS_CFG register (address 00FFh) bit description Default settings are ...
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Integrated Device Technology 11.5.3.2 JESD204A/JESD204B control registers Table 33. IP_STATUS register (address 0801h) bit description Default settings are shown highlighted. Bit Symbol 7 RXSYNC_ERR_FLG RESERVED[5:0] 0 PLL_LOCK Table 34. IP_RESET register (address 0802h) bit description Default settings ...
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Integrated Device Technology Table 36. CFG_SETUP 1101 1110 1111 Table 37. JESD204A/JESD204B configuration table CFG_SETUP[3:0] ADC[0] ADC[1] Lane 0 0 0000 0001 0010 0011 4 0100 5 0101 ON OFF 6 ...
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Integrated Device Technology Table 38. IP_CTRL1 register (address 0805h) bit description Default settings are shown highlighted. Bit Symbol 5 SYNC_POL 4 SYNC_SE 3 EN_RXSYNC_ERR RESERVED Table 39. IP_CTRL2 register (address 0806h) bit description Default settings are shown ...
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Integrated Device Technology Table 43. IP_DEBUG_IN1 register (address 0818h) bit description Default settings are shown highlighted. Bit Symbol PATTERN_IN[15:8] Table 44. IP_DEBUG_IN2 register (address 0819h) bit description Default settings are shown highlighted. Bit Symbol ...
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Integrated Device Technology Table 48. IP_OUTBUF00_SWING register (address 086Bh) bit description Default settings are shown highlighted. Bit Symbol Table 49. IP_OUTBUF01_SWING register (address 086Ch) bit description Default settings are shown highlighted. Bit Symbol RESERVED[4: ...
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Integrated Device Technology Table 51. IP_LANE01_0_CTRL register (address 0872h) bit description Default settings are shown highlighted. Bit Symbol RESERVED[2: LANE_MODE[1:0] 2 LANE_POL 1 RESERVED 0 LANE_PD Table 52. IP_ADC00_0_CTRL register (address 0890h) bit description ...
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Integrated Device Technology 12. Package outline HLQFN56R: plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 1. terminal 1 index area ...
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Integrated Device Technology 13. Abbreviations Table 54. Acronym ADC CDMA DAV ESD FFT GSM ILA IMD3 LSB LTE LVDS DDR LVPECL MIMO MSB OTR SFDR SPI SNR TD-SCDMA WCDMA WiMAX ADC1443D_SER Objective data sheet Dual 14-bit ADC; 125, 160 or ...
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Integrated Device Technology 14. Revision history Table 55. Revision history Document ID Release date ADC1443D_SER v.3.0 20120719 ADC1443D_SER v.2.0 tbd • Modifications: Text and drawings updated throughout entire data sheet. ADC1443_SER v.1.1 20110928 ADC1443D_SER v.1 20110901 15. Contact information For ...
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Integrated Device Technology 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . ...