ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 20

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
11. Application information
ADC1443D_SER
Objective data sheet
11.1.1 Input stage
11.1.2 Common-mode input voltage (V
11.1.3 Pin VCM
11.1 Analog inputs
The analog input of the ADC1443D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with respect to the
common-mode input voltage (V
The equivalent circuit of the sample and hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 26.
The sample phase occurs when the internal sampling clock (derived from the clock signal
on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When
the sampling clock signal becomes LOW, the device enters the hold phase and the
voltage information is transmitted to the ADC core.
Set the common-mode input voltage (V
optimal performance.
When the input stage is AC-coupled, pin VCM can be used to set the common-mode
reference for the analog inputs, for instance, via a transformer middle point. Connect a
0.1 F filter capacitor between pin VCM and ground to ensure a low-noise common-mode
output voltage.
Fig 26. Input sampling circuit
INM
INP
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
PACKAGE
I(cm)
) on pins INP and INM.
ESD
I(cm)
I(cm)
)
) on pins INP and INM externally to 0.9 V for
PARASITICS
ADC1443D series
INTERNAL
INTERNAL
R on = 15 Ω
R on = 15 Ω
CLOCK
CLOCK
SWITCH
SWITCH
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
4 pF
4 pF
001aan472
© IDT 2012. All rights reserved.
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