ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 42

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 38.
Default settings are shown highlighted.
Table 39.
Default settings are shown highlighted.
Table 40.
Default settings are shown highlighted.
Table 41.
Default settings are shown highlighted.
Table 42.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
Bit
5
4
3
2 to 0
Bit
7 to 2
1
0
Bit
7 to 2
1 to 0
Bit
7 to 2
1 to 0
Bit
7 to 0
Symbol
SYNC_POL
SYNC_SE
EN_RXSYNC_ERR
RESERVED
Symbol
RESERVED
SWP_LANE_1_2
SWP_ADC_0_1
Symbol
RESERVED
PRBS_TYPE[1:0]
Symbol
-
PATTERN_OUT[9:8]
Symbol
PATTERN_OUT[7:0]
IP_CTRL1 register (address 0805h) bit description
IP_CTRL2 register (address 0806h) bit description
IP_PRBS_CTRL register (address 080Bh) bit description
IP_DEBUG_OUT1 register (address 0816h) bit description
IP_DEBUG_OUT2 register (address 0817h) bit description
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
Access
-
R/W
Access
-
R/W
Access
R/W
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
Value
0
1
001
Value
0000**
*
Value
000000
00
Value
000000
10
Value
1010 1010
0
*
…continued
Description
synchronization polarity
single-ended synchronization
error reporting using synchronization interface
reserved
Description
reserved
swap lanes: if set to logic 1 the lanes are swapped
symmetrically (L0  L1, L1  L0)
if set to logic 1, ADC 0 and ADC1 are swapped at
the input of the frame assembler
Description
reserved
defines the type of Pseudo-Random Binary
Sequence (PRBS) generator to be used
Description
not used
2 most significant bits of output stage debug word
(inserted just before serializer)
Description
8 least significant bits of output stage debug word
(inserted just before serializer)
0: default synchronization polarity used
(active LOW)
1: polarity inversion (active HIGH)
0: differential synchronization
1: single-ended synchronization
0: disabled
1: enabled
00; PRBS-7; 1 + x
10; PRBS-23; 1 + x
ADC1443D series
6
18
+ x
+ x
1
23
© IDT 2012. All rights reserved.
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