ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 25

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
ADC1443D_SER
Objective data sheet
11.2.2 Equivalent input circuit
11.2.3 Clock input divider
11.2.4 Multi-device synchronization (pins SYSREF, SYSREFN and SYSREFP)
11.3.1 Digital output buffers
11.3 Digital outputs
Figure 34 shows the equivalent circuit of the input clock buffer. The input signal must be
AC-coupled and the common-mode voltage of the differential input stage is set via internal
5 k resistors.
The ADC1443D contains an input clock divider that divides the incoming clock (clock
frequency f
(see bits CLK_DIV[1:0] in Table 23). This feature delivers a higher clock frequency with
better jitter performance, leading to a better SNR result once acquisition has been
performed.
The multi-device synchronization can be controlled with a single-ended or a differential
SYSREF signal.
A high level on SYSREF resets the clock divider phase registers. In a multi-device
application and when the clock divider factor is higher than 1, the ADC1443D
synchronization aligns all sampling clock edges (see Table 8 and Figure 4).
The JESD204A/JESD204B standard specifies that both the receiver and the transmitter
must be provided by the same supply if they are connected in DC-coupling.
Fig 34. Equivalent input circuit
CLKM
CLKP
clk
) by a factor of 1 to 8. it outputs the sampling clock (sampling frequency f
PACKAGE
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
ESD
PARASITICS
5 kΩ
5 kΩ
V
cm(clk)
ADC1443D series
© IDT 2012. All rights reserved.
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