TDA9898HL/V3 NXP [NXP Semiconductors], TDA9898HL/V3 Datasheet - Page 31
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TDA9898HL/V3
Manufacturer Part Number
TDA9898HL/V3
Description
Multistandard hybrid IF processing
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.TDA9898HLV3.pdf
(103 pages)
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NXP Semiconductors
TDA9897_TDA9898_4
Product data sheet
Table 31.
Table 32.
Table 33.
Bit
VAGC
W7[6]
0
0
0
0
0
1
Bit
7 and 6
5 to 0
FSFREQ1
7
Output mode at pin MPP for ATV or radio mode
W5 - data write register bit allocation
W5 - data write register bit description
Symbol
FSFREQ[1:0] DTV filter or sound trap selection for video
SFREQ[5:0]
FSFREQ0
RADIO
W1[7]
X
X
X
0
1
X
6
Rev. 04 — 25 May 2009
Description
synthesizer frequencies; see
SFREQ5
ATV; sound trap; TV = 1; see
00 = M/N standard (4.5 MHz)
01 = B/G standard (5.5 MHz)
10 = I standard (6.0 MHz)
11 = D/K and L/L-accent standard (6.5 MHz)
DTV (low IF); upper BP cut-off frequency; TV = 0; see
Table 17
00 = 7.0 MHz
01 = 8.0 MHz
10 = 9.0 MHz
11 = recommended mode for direct IF; W6[0] = 1
MPPS1
W4[5]
0
0
1
1
1
0
5
SFREQ4
4
MPPS0
W4[4]
0
1
0
1
1
0
SFREQ3
TDA9897; TDA9898
3
Multistandard hybrid IF processing
Table 34
Table 16
Pin MPP output mode
gain control voltage of FM PLL
gain control voltage of SIF amplifier
TAGC monitor voltage
AFC current output, VIF PLL
AFC current output, radio mode
gain control voltage of VIF amplifier
SFREQ2
and
2
and
Table 35
Table 17
SFREQ1
© NXP B.V. 2009. All rights reserved.
1
Table 16
SFREQ0
31 of 103
0
and
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