TDA9898HL/V3 NXP [NXP Semiconductors], TDA9898HL/V3 Datasheet - Page 34
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TDA9898HL/V3
Manufacturer Part Number
TDA9898HL/V3
Description
Multistandard hybrid IF processing
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.TDA9898HLV3.pdf
(103 pages)
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NXP Semiconductors
TDA9897_TDA9898_4
Product data sheet
Table 36.
Table 37.
[1]
Table 38.
Bit
7 and 6 TAGC[1:0]
5 and 4 AGC[2:1]
3
2
1
0
Bit
MOD
W2[7]
0
0
0
0
0
1
1
1
1
TAGC1
7
In TAGC integral loop mode the pin TAGC provides sink and source currents for control. TakeOver Point
(TOP) is set via register TOPNEG W9[4:0].
Symbol
FMWIDE1
TWOFLO
VIDEO1V7 video output level selection; sound carrier trap set to on (W2[0] = 1);
DIRECT
W6 - data write register bit allocation
TAGC0
W6 - data write register bit description
AGC mode and behavior
6
FORCESP
W8[3]
0
0
0
0
1
X
X
X
X
Description
tuner AGC mode
AGC mode and behavior; see
FM window
synthesizer frequency selection
see
direct IF at DTV mode; TV set to DTV (W1[4] = 0); see
Table 17
00 = TAGC integral loop mode; all currents off
01 = TAGC integral loop mode; source current off
10 = TAGC integral loop mode
11 = TAGC derived from IF AGC; recommended for positive modulated
signals
1 = 1 MHz
0 = see
1 = Japan mode (57 MHz)
0 = synthesizer mode
1 = 1.7 V at CVBS
0 = 2.0 V at CVBS
1 = direct IF output
0 = low IF output
AGC2
Rev. 04 — 25 May 2009
Table 22
5
Table 27
AGC2
W6[5]
0
0
1
1
X
0
0
1
1
and
AGC1
[1]
Table 23
4
bit FMWIDE0
FMWIDE1
AGC1
W6[4]
0
1
0
1
X
0
1
0
1
Table 38
3
TDA9897; TDA9898
Multistandard hybrid IF processing
TWOFLO
2
VIF AGC
mode
normal
minimum gain
normal
normal
fast
normal
minimum gain
2nd
2nd fast
VIDEO1V7
Table 16
© NXP B.V. 2009. All rights reserved.
1
SIF AGC
mode
normal
minimum gain
normal
fast
fast
normal
minimum gain
normal
fast
and
DIRECT
34 of 103
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