ADV7150LS135 AD [Analog Devices], ADV7150LS135 Datasheet - Page 23

• Manufacturer Part Number: ADV7150LS135
• Description: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
• Manufacturer: AD [Analog Devices]

COMMAND REGISTER 3 (CR3)
(Address Reg (A7–A0) = 07H)
This register contains a number of control bits as shown in the
diagram. CR3 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR38 and CR39 are both reserved).
The diagram shows the various operations under the control of
CR3. This register can be read from as well written to. In read
mode, CR38 and CR39 are both returned as zeros.
COMMAND REGISTER 3-BIT DESCRIPTION
PRGCKOUT Frequency Control (CR31–CR30)
These bits specify the output frequency of the PRGCKOUT
output. PRGCKOUT is a divided down version of the pixel
CLOCK.
REV. A
*THESE BITS ARE READ-
ONLY RESERVED BITS.
A READ CYCLE WILL
RETURN ZEROS "00."
CR37 CR36
CR39
0
0
1
1
RESERVED*
PIXEL MULTIPLEX CONTROL
0
1
0
1
CR38
1:1 MUXING: LOADOUT = CLOCK
2:1 MUXING LOADOUT = CLOCK
RESERVED
4:1 MUXING :LOADOUT = CLOCK 4
CR37
Command Register 3 (CR3) (CR39–CR30)
CR36
CR35 CR34 CR33 CR32
EXTRA BLANK PIPELINE DELAY CONTROL
(ADDS TO PIXEL PIPELINE DELAY; t
0
0
0
1
·
·
0
0
0
1
·
·
CR35
2
1
–23–
0
0
1
1
·
·
CR34
BLANK Pipeline Delay Control (CR35–CR32)
These bits specify the additional pipeline delay that can be
added to the BLANK function, relative to the overall device
pipeline delay (t
video DAC from a shorter pipeline than the video pixel data,
this control is useful in deskewing the pipeline differential.
Pixel Multiplex Control (CR37–CR36)
These bits specify the device’s multiplex mode. It, therefore,
also determines the frequency of the LOADOUT signal.
LOADOUT is a divided down version of the pixel CLOCK.
Revision Register
(Address Reg (A7–A0) = 0BH)
This register is a read only register containing the revision of
silicon.
0
1
0
1
·
·
CR33
t
t
t
t
PD
PD
PD
PD
+ 1 x LOADOUT
+ 2 x LOADOUT
+ 15 x LOADOUT
PD
CR32
·
·
). As the BLANK control normally enters the
PRGCKOUT FREQUENCY
CR31 CR30
PD
1
0
0
1
)
0
1
0
1
CONTROL
CR31
CLOCK
CLOCK
CLOCK
CLOCK
CR30
16
32
4
8
ADV7150