ADV7150LS135 AD [Analog Devices], ADV7150LS135 Datasheet - Page 4

• Manufacturer Part Number: ADV7150LS135
• Description: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
• Manufacturer: AD [Analog Devices]

NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
ADV7150
TTL input values are 0 to 3 volts, with input rise/fall times
V
puts. Analog output load
SYNCOUT
Temperature range (T
Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B, C, D]; GREEN [A, B, C, D]; BLUE [A, B, C, D], Palette Selects: PS0 [A, B, C, D]; PS1
[A, B, C, D]; Pixel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.
plexing; = CLOCK
These fixed values for Pipeline Delay are valid under conditions where t
lay is increased by 2 additional CLOCK cycles for 2:1 Mode and is increased by 4 additional CLOCK cycles for 4:1 Mode, after calibration is performed.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10%
and 90% points of full-scale transition. Transition time measured from the 50% point of full-scale transition to the output remaining within 2% of the final output
value (Transition time does not include clock and data feedthrough).
t
t
lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t
and as such is independent of external databus loading capacitances.
23
25
5% for all versions.
is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing;
AA
and t
is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
–0.8 V to V
24
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
(4:1 MULTIPLEXING)
(1:1 MULTIPLEXING)
(2:1 MULTIPLEXING)
PIXEL INPUT
30 pF.
AA
LOADIN
–1.8 V, with input rise/fall times
DATA*
LOADOUT
MIN
LOADOUT
LOADOUT
2 = 2
CLOCK
CLOCK
to T
10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I
*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC
MAX
t
1
t
ns. 4:1 Multiplexing; = CLOCK
8
): 0 C to +70 C; T
VALID
DATA
Figure 1. Load Circuit for Databus Access and Relinquish Times
t
9
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK )
t
4
2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
J
(Silicon Junction Temperature)
Figure 3. LOADIN vs. Pixel Input Data
t
5
t
1
3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
TO
OUTPUT
PIN
100pF
4 = 4
10
VALID
DATA
and -t
t
2
t
1
–4–
ns.
11
t
3
are met. If either t
t
6
I
I
SINK
SOURCE
100 C.
25
, quoted in the Timing Characteristics is the true value for the device
+2.1V
10
or -t
t
7
11
are not met, the part will operate but the Pipe line De-
VALID
DATA
= CLOCK = t
1
ns. 2:1 Multi-
PLL
and
REV. A