ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 27

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

External Port Bus Request and Grant Cycle Timing
Table 20
bus grant operations.
Table 20. External Port Bus Request and Grant Cycle Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
These are preliminary timing parameters that are based on worst-case operating conditions.
The pad loads for these timing parameters are 20 pF.
BS
BH
SD
SE
DBG
EBG
DBH
EBH
BR Asserted to CLKOUT High Setup
CLKOUT High to BR Deasserted Hold Time
CLKOUT Low to AMSx, Address and ARE/AWE Disable
CLKOUT Low to AMSx, Address and ARE/AWE Enable
CLKOUT High to BG Asserted Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH Asserted Setup
CLKOUT High to BGH Deasserted Hold Time
and
1, 2
ARE
BR
Figure 12
AMSx
BGH
CLKOUT
ABE3-0
BG
ADDR25-2
AWE
describe external port bus request and
t
BS
Figure 12. External Port Bus Request and Grant Cycle Timing
Rev. B | Page 27 of 64 | June 2007
t
BH
t
t
t
SD
SD
SD
Min
4.6
0.0
t
t
DBG
DBH
Max
4.5
4.5
3.6
3.6
3.6
3.6
t
t
EBG
EBH
ADSP-BF561
t
t
t
SE
SE
SE
Unit
ns
ns
ns
ns
ns
ns
ns
ns