ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 36

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
Serial Peripheral Interface (SPI) Port—
Slave Timing
Table 27
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
DSOE
DSDHI
DDSPID
HDSPID
HSPID
and
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
CPHA=0
CPHA=1
Figure 22
(INPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISS
MOSI
MOSI
(INPUT)
(INPUT)
MISO
MISO
SCK
SCK
describe SPI port slave operations.
t
DSOE
t
DSOE
t
SDSCI
MSB VALID
t
t
t
DDSPID
t
SPICHS
SPICLS
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
MSB VALID
SSPID
t
DDSPID
MSB
t
t
MSB
Rev. B | Page 36 of 64 | June 2007
SPICHS
SPICLS
t
HDSPID
t
HSPID
t
SSPID
t
LSB VALID
DDSPID
t
t
SPICLK
SSPID
LSB
LSB VALID
t
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
HSPID
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
t
DSDHI
– 1.5
– 1.5
t
– 1.5
– 1.5
– 1.5
– 1.5
HDS
LSB
DSDHI
t
HSPID
t
SPITDS
Max
8
8
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns