ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 39

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

Timer Cycle Timing
Table 29
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f
Table 29. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
Switching Characteristic
t
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPIxCLK input pins in PWM output mode.
The minimum time for t
WL
WH
HTO
SCLK
Timer Pulse Width Input Low
Timer Pulse Width Input High
Timer Pulse Width Output
/2 MHz.
CLKOUT
(PWM OUTPUT MODE)
EXTERNAL CLOCK MODES)
and
(WIDTH CAPTURE AND
Figure 25
TMRx
TMRx
HTO
is one cycle, and the maximum time for t
describe timer expired operations. The
2
(Measured in SCLK Cycles)
1
1
(Measured in SCLK Cycles)
(Measured in SCLK Cycles)
Figure 25. Timer PWM_OUT Cycle Timing
Rev. B | Page 39 of 64 | June 2007
t
WL
HTO
equals (2
32
–1) cycles.
t
WH
t
HTO
Min
1
1
1
Max
(2
32
–1)
ADSP-BF561
Unit
SCLK
SCLK
SCLK