ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 35

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

Serial Peripheral Interface (SPI) Port—
Master Timing
Table 26
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
and
CPHA=0
CPHA=1
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISELx Low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Figure 21
(OUTPUT)
(INPUT)
(INPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
(OUTPUT)
SPISELx
(OUTPUT)
(OUTPUT)
MISO
MISO
MOSI
MOSI
SCK
SCK
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
t
SSPIDM
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
MSB
t
t
SPICHM
SPICLM
MSB VALID
t
HSPIDM
Rev. B | Page 35 of 64 | June 2007
t
t
t
DDSPIDM
MSB
SPICLM
SPICHM
t
HSPIDM
t
DDSPIDM
t
HDSPIDM
LSB VALID
t
t
SSPIDM
SPICLK
t
HDSPIDM
LSB VALID
LSB
t
Min
7.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
HDSM
LSB
t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
HSPIDM
– 1.5
– 1.5
– 0.5
– 1.5
– 1.5
– 1.5
t
SPITDM
ADSP-BF561
Max
6
+4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns