ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
Parallel Peripheral Interface Timing
Table
default Parallel Peripheral Interface operations.
Table 21. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
For PPI modes that use an internally generated frame sync, the PPIxCLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
cannot exceed 75 MHz and f
POLC = 0
PPIxCLK
PPIxCLK
POLC = 1
PPIxSYNC11
PPIxSYNC2
PPIxDATA
21, and
PPIxCLK Width
PPIxCLK Period
External Frame Sync Setup Before PPIxCLK
External Frame Sync Hold After PPIxCLK
Receive Data Setup Before PPIxCLK
Receive Data Hold After PPIxCLK
Internal Frame Sync Delay After PPIxCLK
Internal Frame Sync Hold After PPIxCLK
Transmit Data Delay After PPIxCLK
Transmit Data Hold After PPIxCLK
POLS = 1
POLS = 0
POLS = 1
POLS = 0
Figure 13
through
1
1
SCLK
should be equal to or greater than PPIxCLK.
Figure 16 on Page
Figure 13. PPI GP Rx Mode with Internal Frame Sync Timing (Default)
t
HOFSPE
FRAME
SYNC IS
DRIVEN
OUT
30, describe
Rev. B | Page 28 of 64 | June 2007
t
DFSPE
t
SDRPE
DATA0
IS
SAMPLED
t
HDRPE
If bit 4 of the PLL_CTL register is set, then
and
Figure 18 on Page 31
SCLK
/2. For modes with no frame syncs or external frame syncs, PPIxCLK
apply.
Min
5.0
13.3
4.0
1.0
3.5
2.0
1.7
2.0
Figure 17 on Page 30
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns