ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 12

• Manufacturer Part Number: ATAM894X-TNQY
• Description: 8k-flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

5.3
5.3.1
12
Master Reset
ATAM894
Power-on Reset and Brown-out Detection
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter-
nal input clock supervisor stage (see
the interrupt enable flag, the interrupt pending register and the interrupt active register. During
the power-on reset phase the I/O bus control signals are set to reset mode thereby initializing all
on-chip peripherals. All bi-directional ports are set to input mode.
Attention: During any reset phase, the BP20/NTE input is driven towards V
up transistor. This pin must not be pulled down to V
resenting a resistor of less than 150 k .
Releasing the reset results in a short call instruction (opcode C1h) to the EEPROM address
008h. This activates the initialization routine $RESET which in turn has to initialize all necessary
RAM variables, stack pointers and peripheral configuration registers (see
Figure 5-7.
The ATAM894 has a fully integrated power-on reset and brown-out detection circuitry. For reset
generation no external components are needed.
These circuits ensure that the core is held in the reset state until the minimum operating supply
voltage has been reached. A reset condition will also be generated should the supply voltage
drop momentarily below the minimum operating level except when a power down mode is acti-
vated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down
mode the brown-out detection is disabled.
Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC
register.
Reset Configuration
NRST
V
DD
Pull-up
Figure 5-7 on page
SS
CL
during reset by any external circuitry rep-
12). A master reset activation will reset
CL = SYSCL/4
res
Watch-
supervisor
Brown-out
Power-on
Ext. clock
detection
dog
reset
Reset
timer
res
Internal
CWD
ExIn
Table 6-1 on page
V
V
V
reset
V
DD
SS
DD
SS
DD
by a strong pull-
4679D–4BMCU–05/05
23).