ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 33

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ATAM894X-TNQY

Manufacturer Part Number
ATAM894X-TNQY
Description
8k-flash Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
6.3.1.1
4679D–4BMCU–05/05
Timer 1 Control Register 1 (T1C1)
Figure 6-9.
Note:
The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this
divider and the timer 1 input clock source. The timer input can be supplied by the system clock,
the 32-kHz oscillator or via the clock management. If the clock management generates the
SUBCL, the selected input clock from the RC-oscillator, 4-MHz oscillator or an external clock is
divided by 16.
T1C1
T1RM
T1C2
T1C1
T1C0
CL1
T1C1 register
Write of the
* Bit 3 = MSB, Bit 0 = LSB
T1C1
WDC
Bit 3*
T1RM
Timer 1 Restart Mode
Note: if WDL = 0, Timer 1 restart is impossible
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
T1RM T1C2 T1C1 T1C0
Timer 1 and Watchdog
WDL
WDR WDT1 WDT0
Decoder
Decoder
Bit 2
T1C2
3
RES
CL
2
Q1 Q2 Q3 Q4
T1C1
Bit 1
mode control
Watchdog
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
RES
Q5
MUX for watchdog timer
MUX for interval timer
Q6
T1C0
Bit 0
Q8
Q8
Address: '7'hex — Subaddress: '8'hex
Reset value: 1111b
Q11
Q11
Q14
Q14
T1C2
T1MUX
SUBCL
WDCL
T1BP T1IM
Watchdog
Divider/8
Divider
RESET
ATAM894
T1IM=0
T1IM=1
CWD register
Read of the
INT2
T1OUT
RESET
(NRST)
33

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