ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 35

• Manufacturer Part Number: ATAM894X-TNQY
• Description: 8k-flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

6.3.2
6.3.2.1
4679D–4BMCU–05/05
Timer 2
Features
Both these bits control the time interval for the watchdog reset.
Table 6-7.
8/12-bit timer for
Timer 2 can be used as interval timer for interrupt generation, as signal generator or as
baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up
counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cas-
cadable as an 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be
configured as an 8-bit timer and separate a 4-bit prescaler.
The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer
1 output clock or the shift clock of the serial interface. The external input clock T2I is not syn-
chronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than
SYSCL. Furthermore, with that input clock the Timer 2 operates in the power-down mode
SLEEP (CPU core
sleep and OSC-Stop
NSTOP = 0. The 4-bit counter stages of Timer 2 have an additional clock output (POUT).
Its output has a modulator stage that allows the generation of pulses as well as the generation
and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register
data output to generate Bi-phase- or Manchester code.
If the serial interface is used to modulate a bit-stream, the 4-bit stage of Timer 2 has a special
task. The shift register can only handle bit-stream lengths divisible by 8. For other lengths, the
4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out.
If the timer is used for carrier frequency modulation, the 4-bit stage works together with an addi-
tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty
cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable
count of pulses.
• Interrupt, square-wave, pulse and duty cycle generation
• Baud-rate generation for the internal shift register
• Manchester and Bi-phase modulation together with the SSI
• Carrier frequency generation and modulation together with the SSI
WDT1
0
0
1
1
WDT0
Watchdog Time Control Bits
0
1
0
1
sleep and OSC-Stop
Divider
131072
16384
2048
no). All other clock sources supply no clock signal in SLEEP if
512
Delay Time to Reset with
t
in
15.625 ms
= 1/32 kHz
62.5 ms
yes) as well as in POWER-DOWN (CPU core
0.5 s
4 s
Delay Time to Reset with
0.256 ms/0.512 ms
1.024 ms/2.048 ms
t
65.5 ms/131 ms
8.2 ms/16.4 ms
in
= 1/(2/1 MHz)
ATAM894
35