MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 104

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Document Revision History
22 Document Revision History
Table 66
23 Ordering Information
This section presents ordering information for the device discussed in this document, and it shows an
example of how the parts are marked. The information in this document is accurate for revision 3.x silicon
and later (in other words, for devices with part numbers ending in A or B, such as the MPC8347EA or
MPC8347EB). For information on revision 1.1 silicon and earlier versions (MPC8347E/MPC8347), see
the PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications
23.1
Table 67
individual part numbers correspond to a maximum processor core frequency. For available frequencies,
contact your local Freescale sales office. Also the part numbering scheme includes an application modifier
104
Revision
3
2
1
0
provides a revision history of this document.
shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The
Part Numbers Fully Addressed by this Document
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
11/2006
8/2006
4/2006
3/2006
Date
Updated note in introduction.
In
added table footnote to designate rates that apply only to the TBGA package.
In the features list in
400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3In
replicated note from document introduction.
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in
OV
In
In
2 and max = OV
In
2 and max = OV
Updated DDR2 I/O power values in
Removed Table 20, “Timing Parameters for DDR2-400.”
Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Changed Min and Max values for V
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note “It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.”
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” in row AVDD3 changed power supply from “AVDD3” to “—.”
Initial Release
• 266 MHz for PBGA parts for all silicon revisions
Table
Table
Table
Table
DD
– 0.3.
40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =
44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =
5, “MPC8347EA Typical I/O Power Dissipation,” added GVDD 1.8-V values for DDR2;
63, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
Table 69. Document Revision History
DD
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Section 1, “Overview,”
Table
IH
Substantive Change(s)
Table
and VIL in Table 40,“PCI DC Electrical Characteristics.”
39, “JTAG Interface DC Electrical Characteristics,” to
5, “MPC8347EA Typical I/O Power Dissipation.”
corrected DDR data rate to show:
Section 23, “Ordering Information,”
Freescale Semiconductor