MPC8358 FREESCALE [Freescale Semiconductor, Inc], MPC8358 Datasheet - Page 29

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MPC8358

Manufacturer Part Number
MPC8358
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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8.2.2.2
Table 29
Figure 11
Figure 12
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time, VIL(min) to VIH(max)
RX_CLK clock fall time, VIH(max) to VIL(min)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(reference)(state)
t
relative to the t
timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t
going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on
three letters representing the clock of a particular functional. For example, the subscript of t
(M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
MRDVKH
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
provides the MII receive AC timing specifications.
provides the AC test load.
shows the MII receive AC timing diagram.
MII Receive AC Timing Specifications
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)
RXD[3:0]
RX_CLK
RX_DV
RX_ER
Parameter/Condition
MRX
for inputs and t
clock reference (K) going to the high (H) state or setup time. Also, t
Output
Table 29. MII Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Figure 12. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
/ OV
t
MRX
DD
Z
Figure 11. AC Test Load
0
of 3.3 V ± 10%.
= 50 Ω
Valid Data
t
MRXH
Symbol
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
t
t
t
MRXF
MRDXKH
MRDVKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
MRX
1
R
t
MRDXKH
(first two letters of functional block)(signal)(state)
t
L
MRXR
= 50 Ω
10.0
10.0
Min
1.0
1.0
35
for outputs. For example,
MRDXKL
LV
Typ
400
40
DD
MRX
/2
MRX
symbolizes MII receive
clock reference (K)
represents the MII
Max
4.0
4.0
65
Unit
ns
ns
ns
ns
ns
ns
%
29

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