MPC8358 FREESCALE [Freescale Semiconductor, Inc], MPC8358 Datasheet - Page 34

no-image

MPC8358

Manufacturer Part Number
MPC8358
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8358CVRADDDA
Manufacturer:
FREESCAL
Quantity:
246
Part Number:
MPC8358CVRADDDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8358CVRAGDDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8358CVRAGDGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8358CVVADDE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8358CVVADDEA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.5
Table 34
34
At recommended operating conditions with LV
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock cycle duration
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock duty cycle
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
5. Duty cycle reference is LV
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.7.In
RGMII and RTBI timing. For example, the subscript of t
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
will be added to the associated clock signal.
long as the minimum duty cycle is not violated and stretching occurs for no more than three t
transitioned between.
rev2.1 silicon, due to errata, t
maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. Please refer to QE_ENET10 in the device
errata document. UCC1 does meet t
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
GTX_CLK125 reference clock period
presents the RGMII and RTBI AC timing specifications.
RGMII and RTBI AC Timing
Parameter/Condition
RGT
DD
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
/2.
SKRGTKHDX
Table 34. RGMII and RTBI AC Timing Specifications
SKRGTKHDX
DD
minimum is -0.65 ns for UCC2 option 1 and -0.9 for UCC2 option 2, and t
of 2.5 V ± 5%.
minimum for rev2.1 silicon.
t
t
t
t
t
SKRGTKHDX
SKRGTKHDV
t
t
G125H
SKRGDXKH
SKRGDVKH
RGTH
RGTH
Symbol
RGT
t
t
t
t
RGTR
RGTF
G125
RGT
Specifications
/t
/t
/t
represents the TBI (T) receive (RX) clock. Note also that the
RGT
RGT
G125
1
–0.5
Min
1.1
7.2
45
40
47
Typ
8.0
8.0
50
50
RGT
Max
0.75
0.75
of the lowest speed
0.5
2.6
8.8
55
60
53
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
%
%
%
SKRGTKHDV
Notes
4, 5
3, 5
2
3
6

Related parts for MPC8358