MPC8358 FREESCALE [Freescale Semiconductor, Inc], MPC8358 Datasheet - Page 92

• Manufacturer Part Number: MPC8358
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

System Design Information
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
, OV
, GV
, and LV
planes, to enable quick recharging of the smaller chip
DD
DD
DD
DD
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
, GV
, or LV
as required. Unused active high
DD
DD
DD
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
, GV
, LV
, OV
, and GND pins of
DD
DD
DD
DD
the device.
24.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
2
push-pull single-ended driver type (open drain for I
C).
To measure Z
for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV
/2 (see
Figure
54). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
is trimmed until the voltage at the pad equals
P
OV
/2. R
then becomes the resistance of the pull-up devices. R
and R
are designed to be close to each
DD
P
P
N
other in value. Then, Z
= (R
+ R
)/2.
0
P
N
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
92
Freescale Semiconductor