MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 68

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MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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FEC Electrical Characteristics
13 FEC Electrical Characteristics
This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
13.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.
Table 29
Figure 71
68
Num
M1
M2
M3
M4
PHSELn
MII_RX_ER, MII_RX_CLK)
TxClav
UtpClk
TxEnb
provides information on the MII receive signal timing.
UTPB
SOC
shows MII receive signal timing.
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
MII_RX_CLK pulse width low
U5
5
HighZ at MPHY
MPC860 Family Hardware Specifications, Rev. 7
Characteristic
Figure 70. UTOPIA Transmit Timing
Table 29. MII Receive Signal Timing
U2
2
U5
5
U3
U1
3
1
U4
4
35%
35%
Min
5
5
U1
Max
65%
65%
Freescale Semiconductor
HighZ at MPHY
MII_RX_CL
MII_RX_CL
K period
K period
Unit
ns
ns

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