MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 70

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MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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FEC Electrical Characteristics
13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 31
Figure 73
13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 32
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
70
Num
Num
M10
M11
M12
M9
provides information on the MII async inputs signal timing.
provides information on the MII serial management channel signal timing. The FEC functions correctly
shows the MII asynchronous inputs signal timing diagram.
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
MII_TX_CLK (Input)
MII_CRS, MII_COL minimum pulse width
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_CRS, MII_COL
Table 32. MII Serial Management Channel Timing
Figure 72. MII Transmit Signal Timing Diagram
Figure 73. MII Async Inputs Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
Table 31. MII Async Inputs Signal Timing
Characteristic
Characteristic
M5
M6
M7
M9
M8
Min
1.5
Min
10
0
Max
Max
Freescale Semiconductor
25
MII_TX_CLK
period
Unit
Unit
ns
ns
ns

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