LUPA-4000 CYPRESS [Cypress Semiconductor], LUPA-4000 Datasheet - Page 20

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LUPA-4000

Manufacturer Part Number
LUPA-4000
Description
4M Pixel CMOS Image Sensor
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
3.9.2 Start-up sequence
The LUPA-4000 will go in latch up (draw high current) as soon as all power supplies
are turned on at the same time. The sensor will come out of latch-up and start working
normally as soon as it is being clocked. A power supply with a 400 mA limit is
recommended to avoid damage to the sensor. It is recommended to avoid the time that
the device is in the latch-up state, so clocking of the sensor should start as soon as
possible (i.e. as soon as the system is turned on).
In order to completely avoid latch-up of the image sensor, the next sequence should
be taken into account:
3.9.3 Biasing and analog signals
The analog output levels that may be expected are between 0.3V for a white,
saturated, pixel and 1.3V for a black pixel.
2 Output stages are foreseen, each consisting of 2 output amplifiers, resulting in 4
outputs. 1 Output amplifier is used for the analog signal resulting from the pixels.
The second amplifier is used for a dc reference signal. The dc-level from the buffer is
defined by a DAC, which is controlled by a 7-bit word downloaded in the SPI.
Additionally, an extra bit in the SPI defines if 1 output or the 2 output stages are used.
Table 10 summarizes the biasing signals required to drive this image sensor. For
optimisation reasons of the biasing of the column amplifiers with respect to power
dissipation, we need several biasing resistors. This optimisation results in an increase
of signal swing and dynamic range.
Signal
Out_load
dec_x_load
muxbus_load
nsf_load
Contact:
Cypress Semiconductor Corporation
LUPA-4000
Data Sheet
o Apply Vdd
o Apply clocks and digital pulses to the sensor
o Count 2048 clock_x and 2048 clock_y pulses to empty the shift
o Apply other supplies
info@Fillfactory.com
registers
Comment
Connect with 60 K
Voo and capacitor of
100 nF to Gnd
Connect with 2 M
Vdd and capacitor of
100 nF to Gnd
Connect with 25 K
Vaa and capacitor of
100 nF to Gnd
Connect with 5 K
Vaa and capacitor of
100 nF to Gnd
Table 10: Overview of bias signals
Document #: 38-05712 Rev.**(Revision 1.2 )
3901 North First Street
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Related module
Output stage
X-addressing
Multiplex bus
Column amplifiers
San Jose, CA 95134
DC-level
0.7 V
0.4 V
0.8 V
1.2 V
Page 20 of 49
408-943-2600

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