PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 163
PIC18F2331
Manufacturer Part Number
PIC18F2331
Description
28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2331.pdf
(396 pages)
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16.1
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
• Edge-trigger, period or pulse width measurement
• Programmable prescaler on every input capture
• Special event trigger output (IC1 only)
• Selectable noise filters on each capture input
FIGURE 16-2:
2003 Microchip Technology Inc.
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
operating modes for each channel
channel
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
velcap
CAP1 Pin
(2)
Input Capture
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
FLTCK<2:0>
VELM
Noise
Filter
1
0
MUX
3
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
Prescaler
CAP1M<3:0>
1, 4, 16
Q Clocks
Clock/
Reset/
Interrupt
Decode
Logic
4
Select
Mode
and
Q clocks
CAP1M<3:0>
PIC18F2331/2431/4331/4431
Preliminary
First Event
Reset
CAP1BUF_clk
Input channel (IC1) includes a special event trigger
that can be configured for use in Velocity Measure-
ment mode. Its block diagram is shown in Figure 16-2.
IC2 and IC3 are similar, but lack the special event trig-
ger features or additional velocity-measurement logic.
A
Figure 16-3. Please note that the time base is Timer5.
Special
Event
Reset
IC1_TR
IC1IF
representative
Timer5 Logic
block
CAP1BUF/VELR
diagram
TMR5
Timer
Reset
Control
DS39616B-page 161
Reset
Control
(1)
Timer5 Reset
is
Clock
shown
Reset
in
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