PIC18F2331 MICROCHIP [Microchip Technology], PIC18F2331 Datasheet - Page 205

• Manufacturer Part Number: PIC18F2331
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 17-20:
17.10.3
Figure 17-21 shows an example of a waveform that
might be generated using the PWM output override
feature. The figure shows a six-step commutation
sequence for a BLDC motor. The motor is driven
through a 3-phase inverter as shown in Figure 17-16.
When the appropriate rotor position is detected, the
PWM outputs are switched to the next commutation
state in the sequence. In this example, the PWM out-
puts are driven to specific logic states. The OVDCOND
and OVDCONS register values used to generate the
signals in Figure 17-21 are given in Table 17-4.
REGISTER 17-6:
 2003 Microchip Technology Inc.
POUT0
POUT1
PWM1
PWM0
OUTPUT OVERRIDE EXAMPLES
bit 7-0
Assume: PVOD0 = 0; PVOD1 = 0; PMOD0 = 0
1.
2.
3.
4.
5.
6.
7.
OVERRIDE BITS IN COMPLEMENTARY MODE
OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER
Even override bits have no effect in Complementary mode.
Odd override bit is activated, which causes the even PWM to deactivate.
Dead time insertion.
Odd PWM activated after the dead time.
Odd override bit is deactivated, which causes the odd PWM to deactivate.
Dead time insertion.
Even PWM is activated after the dead time.
POVD7:POVD0: PWM Output Override bits
1 = Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM
0 = Output on PWM I/O pin is controlled by the value in the corresponding POUT bit.
Note
Legend:
R = Readable bit
-n = Value at POR
bit 7
POVD7
R/W-1
time base.
1
(1)
1: Unimplemented in PIC18F2X31 devices; maintain these bits clear.
POVD6
R/W-1
(1)
PIC18F2331/2431/4331/4431
POVD5
R/W-1
Preliminary
W = Writable bit
‘1’ = bit is set
2
POVD4
R/W-1
The PWM Duty Cycle registers may be used in con-
junction with the OVDCOND and OVDCONS registers.
The Duty Cycle registers control the average voltage
across the load and the OVDCOND and OVDCONS
registers
Figure 17-22 shows the waveforms, while Table 17-4
and Table 17-5 show the OVDCOND and OVDCONS
register values used to generate the signals.
3
4
(1)
POVD3
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
control
POVD2
the
R/W-1
commutation
x = bit is unknown
POVD1
R/W-1
DS39616B-page 203
6
5
7
sequence.
POVD0
R/W-1
bit 0