LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 11

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

SDATA_OUT
LINE_OUT_R
MONO_OUT
SDATA_IN
XTL_OUT
BIT_CLK
XTL_IN
Name
SYNC
Name
Pin
10
2
3
5
6
8
Pin
36
37
I / O
I/O
I / O
O
O
I
I
I
O
O
24.576 MHz crystal or oscillator input
To complete the oscillator circuit use a fundamental mode crystal operating in parallel resonance
and connect a 1MΩ resistor across pins 2 and 3. Choose the load capacitors (Figure 2, C1, C2) to
suit the load capacitance required by the crystal (e.g. C1 = C2 = 33 pF for a 20 pF crystal Assumes
that each 'Input + trace' capacitance = 7 pF).
This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at standard
logic levels (V
This pin is only used when the codec is in Primary mode. It may be left open (NC) for any Secondary
mode.
24.576 MHz crystal output
Used with XTAL_IN to configure a crystal oscillator.
When the codec is used with an external oscillator this pin should be left open (NC).
When the codec is configured in a Secondary mode this pin is not used and may be left open (NC).
Input to codec
This is the input for AC Link Output Frames from an AC '97 Digital Audio Controller to the LM4546A
codec. These frames can contain both control data and DAC PCM audio data. This input is sampled
by the LM4546A on the falling edge of BIT_CLK.
AC Link clock
An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC Link.
The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal input
(XTL_IN).
This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and
would normally use the AC Link clock generated by a Primary Codec.
Output from codec
This is the output for AC Link Input Frames from the LM4546A codec to an AC '97 Digital Audio
Controller. These frames can contain both codec status data and PCM audio data from the ADCs.
The LM4546A clocks data from this output on the rising edge of BIT_CLK.
AC Link frame marker and Warm Reset
This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In
normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is
sampled on the rising edge of BIT_CLK and the codec takes the first positive sample of SYNC as
defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK
periods of the frame start it will be ignored.
SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset
is used to clear a power down state on the codec AC Link interface.
Functional Description
Right Stereo Channel Output
This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from
MIX2 via the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along with
LINE_OUT_L) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.
Mono Output
This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2,
after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1.
The optional National 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in
the General Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register.
MIX=0 selects a microphone input. Output level can be muted or adjusted from 0 dB to -46.5 dB
in 1.5 dB steps via the Mono Volume register, 06h.
200308 Version 5 Revision 1
IH
DIGITAL I/O AND CLOCKING
, V
IL
).
Print Date/Time: 2009/07/15 15:26:52
11
Functional Description
www.national.com