LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 24

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

www.national.com
Improving System Performance
The audio codec is capable of dynamic range performance in
excess of 90 db., but the user must pay careful attention to
several factors to achieve this. A primary consideration is
keeping analog and digital grounds separate, and connecting
them together in only one place. Some designers show the
connection as a zero ohm resistor, which allows naming the
nets separately. Although it is possible to use a two layer
board, it is recommended that a minimum of four layers be
used, with the two inside layers being analog ground and dig-
ital ground. If EMI is a system consideration, then as many as
eight layers have been successfully used. The 12 and 25
MHz. clocks can have significant harmonic content depend-
ing on the rise and fall times. With the exception of the digital
VDD pins, (covered later) bypass capacitors should be very
close to the package. The analog VDD pins should be sup-
plied from a separate regulator to reduce noise. By operating
the digital portion on 3.3V instead of 5V, an additional 0.5-0.7
db improvement can be obtained.
Depending on power supply layout, routing, and capacitor
ESR, a device instability can occur, resulting in increased
noise on the outputs. This can be eliminated by adding an
inductor in the digital supply line between the supply bypass
capacitors and the DVDD pins, which increases the high fre-
quency impedance of the supply as seen by the part. This
“current starving” technique slows down internal rise and fall
times, which will improve the signal to noise ratio, especially
at low temperatures. In addition, the EMI radiated from the
board is also reduced.
Multiple Codecs
EXTENDED AC LINK
Up to four codecs can be supported on the extended AC Link.
These multiple codec implementations should run off a com-
mon BIT_CLK generated by the Primary Codec. All codecs
share the AC '97 Digital Controller output signals, SYNC,
SDATA_OUT, and RESET#. Each codec, however, supplies
its own SDATA_IN signal back to the controller, with the result
that the controller requires one dedicated input pin per codec
(Figure 9).
By definition there can be one Primary Codec and up to three
Secondary Codecs on an extended AC Link. The Primary
Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Sec-
ondary Codecs take identities equal to 01, 10 or 11. The
Codec Identity is used as a chip select function. This allows
the Command and Status registers in any of the codecs to be
individually addressed although the access mechanism for
Secondary Codecs differs slightly from that for a Primary.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are in-
ternally pulled up to DV
configured as 'Primary' either by leaving ID1#, ID0# open
(NC) or by strapping them externally to DV
The difference between Primary and Secondary codec
modes is in their timing source and in the Tag Bit handling in
SLOT 0: TAG bits in Output Frames (controller to codec)
Frame
Bit 15
Valid
Slot 1
Valid
14
Slot 2
Valid
13
Slot 3
DD
Valid
12
. The Codec may therefore be
Slot 4
Valid
11
200308 Version 5 Revision 1
DD
10
X
(Digital Supply).
X
9
X
8
Print Date/Time: 2009/07/15 15:26:52
24
X
7
Output Frames for Command/Status register access. For a
timing source, a Primary codec divides down by 2 the fre-
quency of the signal on XTAL_IN and also generates this as
the BIT_CLK output for the use of the controller and any Sec-
ondary codecs. Secondary codecs use BIT_CLK as an input
and as their timing source and do not use XTAL_IN or
XTAL_OUT. The use of Tag Bits is described below.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag
bits for Command Address and Data in the Output Frame as
invalid (i.e. equal to 0). The Command Address and Data tag
bits are in slot 0, bits 14 and 13 and Output Frames are those
in the SDATA_OUT signal from controller to codec. The con-
troller must also place the non-zero value (01, 10, or 11)
corresponding to the Identity (ID1, ID0) of the target Sec-
ondary Codec into the Codec ID field (slot 0, bits 1 and 0) in
that same Output Frame. The value set in the Codec ID field
determines which of the three possible Secondary Codecs is
accessed. Unlike a Primary Codec, a Secondary Codec will
disregard the Command Address and Data tag bits when
there is a match between the 2-bit Codec ID value (slot 0, bits
1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the
Codec-ID/Identity match to indicate that the Command Ad-
dress in slot 1 and (if a “write”) the Command Data in slot 2
are valid.
When reading from a Secondary Codec, the controller must
send the correct Codec ID bits (i.e. the target Codec Identity
in slot 0, bits 1 and 0) along with the read-request bit (slot 1,
bit 19) and target register address (slot 1, bits 18 – 12). To
write to a Secondary Codec, a controller must send the cor-
rect Codec ID bits when slot 1 contains a valid target register
address and “write” indicator bit and slot 2 contains valid tar-
get register data. A write operation is only valid if the register
address and data are both valid and sent within the same
frame. When accessing the Primary Codec, the Codec ID bits
are cleared and the tag bits 14 and 13 resume their role indi-
cating the validity of Command Address and Data in slots 1
and 2.
The use of the tag bits in Input Frames (carried by the
SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the inverting input pins
ID1#, ID0# (pins 46 and 45) and can be read as the value of
the ID1, ID0 bits (D15, D14) in the Extended Audio ID register,
28h of the target codec.
Slots in the AC Link Output Frame are always mapped to carry
data to the left DAC channel in slot 3 and data to the right DAC
channel in slot 4. Similarly, slots in AC Link Input Frames are
always mapped such that PCM data from the left ADC chan-
nel is carried by slot 3 and PCM data from the right ADC
channel by slot 4. Output Frames are those carried by the
SDATA_OUT signal from the controller to the codec while In-
put Frames are those carried by the SDATA_IN signal from
the codec to the controller.
X
6
X
5
X
4
3
X
2
X
ID1
1
ID0
0