LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 16

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

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AC Link Serial Interface Protocol
AC LINK OUTPUT FRAME:
SDATA_OUT, CONTROLLER OUTPUT TO LM4546A INPUT
The AC Link Output Frame carries control and PCM data to
the LM4546A control registers and stereo DAC. Output
Frames are carried on the SDATA_OUT signal which is an
output from the AC '97 Digital Controller and an input to the
LM4546A codec. As shown in Figure 3, Output Frames are
constructed from thirteen time slots: one Tag Slot followed by
twelve Data Slots. Each Frame consists of 256 bits with each
of the twelve Data Slots containing 20 bits. Input and Output
Frames are aligned to the same SYNC transition. Note that
since the LM4546A is a two channel codec, it only accepts
data in 4 of the twelve Data Slots – 2 for control, one each for
PCM data to the left and right channel DACs. Data Slot 3 & 4
are used to stream data to the stereo DAC for all modes se-
lected by the Identity pins ID1#, ID0#.
A new Output Frame is signaled with a low-to-high transition
of SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 4 and Figure
5, the first tag bit in the Frame (“Valid Frame”) should be
clocked from the controller by the next rising edge of BIT_CLK
200308 Version 5 Revision 1
FIGURE 3. AC Link Bidirectional Audio Frame
FIGURE 4. AC Link Output Frame
Print Date/Time: 2009/07/15 15:26:52
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and sampled by the LM4546A on the following falling edge.
The AC '97 Controller should always clock data to
SDATA_OUT on a rising edge of BIT_CLK and the LM4546A
always samples SDATA_OUT on the next falling edge. SYNC
is sampled with the rising edge of BIT_CLK.
The LM4546A checks each Frame to ensure 256 bits are re-
ceived. If a new Frame is detected (a low-to-high transition on
SYNC) before 256 bits are received from the old Frame then
the new Frame is ignored i.e. the data on SDATA_OUT is
discarded until a valid new Frame is detected.
The LM4546A expects to receive data MSB first, in an MSB
justified format.
SDATA_OUT: Slot 0 – Tag Phase
The first bit of Slot 0 is designated the "Valid Frame" bit. If this
bit is 1, it indicates that the current Output Frame contains at
least one slot of valid data and the LM4546A will check further
tag bits for valid data in the expected Data Slots. With the
codec in Primary mode, a controller will indicate valid data in
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