LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 17

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

a slot by setting the associated tag bit equal to 1. Since it is a
two channel codec the LM4546A can only receive data from
four slots in a given frame and so only checks the valid-data
bits for 4 slots. In Primary mode these tag bits are for: slot 1
(Command Address), slot 2 (Command Data), slot 3 (PCM
data for left DAC) and slot 4 (PCM data for right DAC).
The last two bits in the Tag contain the Codec ID used to se-
lect the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the controller
would not access a secondary codec unless it was providing
valid Command Address and/or Data. When in one of the
secondary modes the LM4546A only checks the tag bits for
the Codec ID and for valid data in the two audio data slots 3
& 4.
When sending an Output Frame to a Secondary mode codec,
a controller should set tag bits 14 and 13 to zero.
Bit
15
14
13
12
11
FIGURE 5. Start of AC Link Output Frame
Left DAC data in
Control register
Control register
Right DAC data
Description
Valid Frame
address
in Slot 4
Slot 3
data
SLOT 0, OUTPUT FRAME
1 = Valid data in at least one
1 = Valid Control Address in
1 = Valid Control Data in Slot 2
1 = Valid PCM Data in Slot 3
1 = Valid PCM Data in Slot 4
slot.
Slot 1 (Primary codec only)
(Primary codec only)
(Primary & all Secondary
modes)
(Primary & all Secondary
modes)
200308 Version 5 Revision 1
Comment
20030805
Print Date/Time: 2009/07/15 15:26:52
17
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4546A and whether the access op-
eration is a register read or register write. The MSB of slot 1
(bit 19) is set to 1 to indicate that the current access operation
is 'read'. Bits 18 through 12 are used to specify the 7-bit reg-
ister address of the read or write operation. The least signifi-
cant twelve bits are reserved and should be stuffed with zeros
by the AC '97 controller.
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4546A
when the access operation is 'write'. The least significant four
bits should be stuffed with zeros by the AC '97 controller. If
the access operation is a register read, the entire slot, bits 19
through 0 should be stuffed with zeros.
SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right
Channels
Slots 3 and 4 are 20-bit fields used to transmit PCM data to
the left and right channels of the stereo DAC for all codec
Primary and Secondary modes. Any unused bits should be
stuffed with zeros. The LM4546A DACs have 18-bit resolution
and will therefore use the 18 MSBs of the 20-bit PCM data
(MSB justified).
SDATA_OUT: Slots 5 to 12 – Reserved
These slots are not used by the LM4546A and should all be
stuffed with zeros by the AC '97 Controller.
18:12
10:2
Bits
11:0
Bits
19:4
Bits
19:0
Bit
1,0
3:0
19
Control Register
PCM DAC Data
Description
Description
Description
Description
Read/Write
(Left /Right
Write Data
Channels)
(ID1, ID0)
Reserved
Reserved
Not Used
Codec ID
Register
Address
SLOTS 3 & 4, OUTPUT FRAME
SLOT 1, OUTPUT FRAME
SLOT 2, OUTPUT FRAME
Controller should stuff these
slots with “0”s
The codec ID is used in a multi-
codec system to identify the
target Secondary codec for the
Control Register address and/or
data sent in the Output Frame
1 = Read
0 = Write
Identifies the Status/Command
register for read/write
Controller should set to "0"
Controller should stuff with zeros
if operation is “read”
Set to "0"
Slots used to stream data to
DACs for all Primary or
Secondary modes.
Set unused bits to "0"
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