LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 22

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

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lection mux and LPBK which connects the output of the stereo
ADC to the input of the stereo DAC. LPBK provides a mixed-
mode analog and digital loopback path between analog inputs
and analog outputs.
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC '97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem
readiness and also to program the LM4546A powerdown
states. The 4 LSBs indicate status and 6 of the 8 MSBs control
powerdown.
The 4 LSBs of this register indicate the status of the 4 audio
subsections of the codec: Reference voltage, Analog mixers
and amplifiers, DAC section, ADC section. When the "Codec
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:
slot 0, bit 15) is a "1", it indicates that the AC Link and AC '97
registers are in a fully operational state and that control and
status information can be transferred. It does not indicate that
the codec is ready to send or receive audio PCM data or to
pass signals through the analog I/O and mixers. To determine
that readiness, the Controller must check that the 4 LSBs of
this register are set to “1” indicating that the appropriate audio
subsections are ready.
The powerdown bits PR0 – PR5 control internal subsections
of the codec. They are implemented in compliance with AC
'97 Rev 2 to support the standard device power management
states D0 – D3 as defined in the ACPI and PCI Bus Power
Management specification.
PR0 controls the powerdown state of the ADC and associated
sampling rate conversion circuitry. PR1 controls powerdown
for the DAC and the DAC sampling rate conversion circuitry.
PR2 powers down the mixer circuits (MIX1, MIX2, National
3D Sound, Mono Out, Line Out). PR3 powers down V
addition to all the same mixer circuits as PR2. PR4 powers
down the AC Link digital interface – see Figure 8 for signal
powerdown timing. PR5 disables internal clocks. PR6 and
PR7 are not used.
Default: 0000h
LPBK
POP
MIX
BIT
MS
3D
PCM Out Path:
National 3D Sound:
Mono output select:
Mic select:
ADC/DAC Loopback:
Function
200308 Version 5 Revision 1
*0 = 3D allowed
*0 = off
*0 = Mix
*0 = MIC1
*0 = No Loopback
1 = 3D bypassed
1 = on
1 = Mic
1 = MIC2
1 = Loopback
REF
in
Print Date/Time: 2009/07/15 15:26:52
22
EXTENDED AUDIO ID REGISTER (28h)
This read-only register identifies which AC '97 Extended Au-
dio features are supported. The LM4546A features VRA
(Variable Rate Audio) and ID1, ID0 (Multiple Codec support).
VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and ID0,
show the current Codec Identity as defined by the Identity pins
ID1#, ID0# (pins 46 and 45). Note that the external logic con-
nections to ID1#, ID0# (pins 46 and 45) are inverse in polarity
to the value of the Codec Identity (ID1, ID0) held in bits D15,
D14. Codec mode selections are shown in the table below.
EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4546A. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate for
the left and right channels of the DAC (PCM DAC Rate, 2Ch)
and the ADC (PCM ADC Rate, 32h). When Variable Rate
Audio is enabled via bit 0 of the Extended Audio Control/Sta-
tus register (2Ah), the sample rates can be programmed, in 1
Default: 000Xh
NC/DV
NC/DV
Default: 0000h
Pin 46
(ID1#)
GND
GND
BIT#
BIT#
VRA
BIT
10
11
12
13
14
15
0
1
2
3
8
9
DD
DD
NC/DV
NC/DV
Pin 45
(ID0#)
*0 = VRA off (Frame-rate sampling)
GND
GND
1 = VRA on
ADC
DAC
ANL
REF
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
BIT
BIT
DD
DD
D15,28h
(ID1)
Not Used
Not Used
1 = ADC section ready to
1 = DAC section ready to accept
1 = Analog mixers ready
1 = V
1 = Powerdown ADCs and
1 = Powerdown DACs
1 = Powerdown Analog Mixer
1 = Powerdown Analog Mixer
1 = Powerdown AC Link digital
1 = Disable Internal Clock
0
0
1
1
Function: Powerdown
transmit data
data
Record Select Mux
(V
(V
interface (BIT_CLK off)
Function
REF
Function: Status
REF
REF
D14,28h
(ID0)
is up to nominal level
0
1
0
1
still on)
off)
Codec Identity
Primary
Secondary 1
Secondary 2
Secondary 3
Mode