PIC18F242 MICROCHIP [Microchip Technology], PIC18F242 Datasheet - Page 65

• Manufacturer Part Number: PIC18F242
• Description: 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

EXAMPLE 5-3:
5.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.
TABLE 5-2:
© 2006 Microchip Technology Inc.
Address
FF8h
FF7h
FF6h
FF5h
FF2h
FA7h
FA6h
FA2h
FA1h
FA0h
Legend:
PROGRAM_MEMORY
Required
Sequence
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Shaded cells are not used during FLASH/EEPROM access.
x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'.
Name
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DECFSZ COUNTER_HI
BRA
BCF
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Program Memory Table Latch
EEPROM Control Register2 (not a physical register)
EEPGD
GIEH
Bit 7
GIE/
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
—
—
—
—
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
PROGRAM_LOOP
EECON1,WREN
CFGS
PEIE/
Bit 6
GIEL
—
—
—
—
TMR0IE
Bit 5
bit21
—
—
—
—
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
FREE
INTE
EEIP
EEIE
Bit 4
EEIF
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
5.5.4
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed.
(Section 19.0) for more detail.
5.6
See “Special Features of the CPU” (Section 19.0) for
details on code protection of FLASH program memory.
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
Bit 2
FLASH Program Operation During
Code Protection
See
TMR3IP
TMR3IF
TMR3IE
PROTECTION AGAINST SPURIOUS
WRITES
INTF
Bit 1
WR
“Special
CCP2IP
CCP2IE
CCP2IF
RBIF
Bit 0
RD
PIC18FXX2
Features
--00 0000 --00 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
---0 0000 ---0 0000
---0 0000 ---0 0000
POR, BOR
Value on:
—
DS39564C-page 63
of
the
Value on
RESETS
All Other
—
CPU”