ADV212 AD [Analog Devices], ADV212 Datasheet - Page 21

• Manufacturer Part Number: ADV212
• Description: JPEG 2000 Video Codec
• Manufacturer: AD [Analog Devices]

Table 16. Pin Function Descriptions
Pin No.
119
117
37 to 34,
27 to 25,
16, 15, 24,
14 to 12,
2, 6, 5
88, 107,
87, 97
96
95
86
85
76
121-Ball Package
Location
L9
L7
D4 to D1,
C5 to C3,
B5, B4, C2,
B3 to B1,
A2, A6, A5
H11, K8,
H10, J9
J8
J7
H9
H8
G10
Pin No.
132
131
64, 49 to 51,
37 to 39, 25
to 27, 13 to
15, 2 to 4
108 to 106,
96
95
94
84
83
82
144-Ball Package
Location
L12
L11
F4, E1 to E3,
D1 to D3,
C1 to C3,
B1 to B3,
A2 to A4
J12, J11,
J10, H12
H11
H10
G12
G11
G10
Mnemonic
MCLK
RESET
HDATA
[15:0]
ADDR [3:0]
CS
WE
RDFB
RD
WEFB
ACK
IRQ
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1
1
2
3
Pins
Used
1
1
16
4
1
1
1
1
1
Type
I
I
I/O
I
I
I
I
O
O
Description
System Input Clock. See the PLL section.
Reset. Causes the ADV212 to immediately reset.
CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1
must be held high when a RESET is applied.
Host Data Bus. With HDATA [23:16],
HDATA [27:24], and HDATA [31:28], these pins
make up the 32-bit wide host data bus. The
async host interface is interfaced together
with ADDR[3:0], CS, WE, RD, and ACK.
Unused HDATA pins should be pulled down
via a 10 kΩ resistor.
Address Bus for the Host Interface.
Chip Select. This signal is used to qualify
addressed read and write access to the
ADV212 using the host interface.
Write Enable Used with the Host Interface.
Read Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of WE and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
Read Enable Used with the Host Interface.
Write Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of RD and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
Acknowledge. Used for direct register accesses.
This signal indicates that the last register access
was successful. Due to synchronization issues,
control and status register accesses might incur
an additional delay; therefore, the host software
should wait for acknowledgment from the
ADV212 before attempting another register
access.
Accesses to the FIFOs (external DMA modes),
on the other hand, are guaranteed to occur
immediately, provided that space is available;
therefore, the host software does not need to
wait for ACK before attempting another register
access, provided that the timing constraints
are observed.
If ACK is shared with more than one device, ACK
should be connected to a pull-up resistor (10 kΩ)
and the PLL_HI register, Bit 4, must be set to 1.
Interrupt. This pin indicates that the ADV212
requires the attention of the host processor.
This pin can be programmed to indicate the
status of the internal interrupt conditions
within the ADV212. The interrupt sources are
enabled via the bits in register EIRQIE.
ADV212