ADV212 AD [Analog Devices], ADV212 Datasheet - Page 34

• Manufacturer Part Number: ADV212
• Description: JPEG 2000 Video Codec
• Manufacturer: AD [Analog Devices]

ADV212
APPLICATIONS
This section describes typical video applications for the
ADV212 JPEG 2000 video processor.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 23), an 1080i
application requires at least two ADV212s to encode or decode
full-resolution 1080i video. In encode mode, the ADV212
accepts Y and CbCr data on separate buses. An encode example
is shown in Figure 33.
32-BIT HOST CPU
DATA[31:0]
ADDR[3:0]
DREQ
DACK
DREQ
DACK
G I/O
ACK
ACK
IRQ
IRQ
WR
WR
CS
RD
CS
RD
Figure 33. Encode—Multichip Application
HDATA[31:0]
ADDR[3:0]
CS
RD
ACK
WE
IRQ
DREQ
DACK
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
ADV212_1_SLAVE
ADV212_2_SLAVE
VDATA[11:2]
VDATA[11:2]
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VSYNC
HSYNC
HSYNC
VSYNC
MCLK
FIELD
MCLK
FIELD
VCLK
VCLK
CbCr
In decode mode, a master/slave configuration (as shown in
Figure 34) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV212s. See the
Application Note
in a multichip application.
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV212 outputs.
74.25MHz
OSC
CbCr
Y
LLC
Y[9:0]
C[9:0]
10-BIT SD/HD
ADV7402
for details on how to configure the ADV212s
DECODER
VIDEO
1080i
VIDEO IN
AN-796