ADV212 AD [Analog Devices], ADV212 Datasheet - Page 22

• Manufacturer Part Number: ADV212
• Description: JPEG 2000 Video Codec
• Manufacturer: AD [Analog Devices]

ADV212
Pin No.
63
64
65
75
90 to 92, 78
79 to 81, 70
121-Ball Package
Location
F8
F9
F10
G9
J2 to J4, H1
H2 to H4, G4
Pin No.
72
71
70
69
111,97 to 99
100, 85 to 87
144-Ball Package
Location
F12
F11
F10
F9
K3, J1 to J3
J4, H1 to H3
Mnemonic
DREQ0
FSRQ0
VALID
CFG1
DACK0
HOLD
FCS0
DREQ1
FSRQ1
CFG2
DACK1
FCS1
HDATA
[31:28]
JDATA [7:4]
HDATA
[27:24]
JDATA [3:0]
Rev. 0 | Page 22 of 44
Pins
Used
1
1
1
1
4
4
Type
O
O
O
I
I
I
I
O
O
I
I
I
I/O
I/O
I/O
I/O
Description
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 0.
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream.
Polarity of this pin is programmable in the
EDMOD0 register. VALID is always an output.
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ0) has been
acknowledged and that the data transfer can
proceed. This pin must be held high at all
times if the DMA interface is not used, even if
the DMA channels are disabled.
External Hold Indication for JDATA Input/Output
Stream. Polarity is programmable in the
EDMOD0 register. This pin is always an input.
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 0
(asynchronous mode).
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed.
This pin must be held high at all times unless a
DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA channels
are disabled.
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).