PALCE26V12 AMD [Advanced Micro Devices], PALCE26V12 Datasheet
PALCE26V12
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PALCE26V12 Summary of contents
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... Varied product term distribution allows product terms per output GENERAL DESCRIPTION The PALCE26V12 is a 28-pin version of the popular PAL22V10 architecture. Built with low-power, high- speed, electrically-erasable CMOS technology, the PALCE26V12 offers many unique advantages. Device logic is automatically configured according to the user’ ...
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... I 12 PROGRAMMABLE AND ARRAY (52x150 MACRO MACRO MACRO MACRO I/O 3 I/O 4 I PALCE26V12 Family MACRO MACRO MACRO MACRO I/O 7 I/O 8 I/O 9 I/O 10 PLCC ...
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... CC Valid Combinations PALCE26V12H-7 JC PALCE26V12H-10 PC, JC, PI, JI PALCE26V12H-15 PALCE26V12H-20 2–308 PALCE26V12H-7/10/15/20 (Com’l), H-10/15/20 (Ind) PAL Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released /4 combinations ...
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... S . Figure 1. PALCE26V12 Macrocell Registered or Combinatorial ( see Table 1). Each macrocell of the PALCE26V12 includes a D-type (1) through a CC flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH edge of the selected clock input. Any macrocell can be configured as combinatorial by selecting a multiplexer path that bypasses the flip-flop ...
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... Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE26V12 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and ...
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... D Q CLK Q SP Registered Active-Low I/O Registered Outputs Combinatorial Active-Low I CLK Q SP Combinatorial Active-Low Output, Register Feedback Combinatorial Outputs Figure 2. PALCE26V12 Macrocell Configuration Options PALCE26V12 Family CLK Q SP Registered Active-High Output, Register Feedback CLK Q SP Registered Active-High I/O Combinatorial Active-High I/O ...
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... When (unprogrammed) the feedback is selected When (programmed), the feedback is the opposite of 3 that selected 2–312 PALCE26V12 PALCE26V12 Family 48 ASYNCH. RESET ...
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... When (unprogrammed) the feedback is selected When (programmed), the feedback is the opposite of 3 that selected PALCE26V12 PALCE26V12 Family AMD AR CLK 1 SP CLK I ...
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... Outputs Open (I IN OUT V = Max MHz Outputs Open (I IN OUT VCC = Max MHz and I (or I and OZL IH OZH PALCE26V12H-7/10 (Com’l), H-10 (Ind + +4. +5. – +5.5 V Min Max 2.4 IL ...
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... calculated value and is not guaranteed can be found using the following equation 1/f MAX (internal feedback) – Test Conditions OUT 1/(tS + tCO) 1/(tS + tCF) PALCE26V12H-7/10 (Com’l), H-10 (Ind) AMD Typ MHz 8 ...
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... Max MHz Outputs Open (I IN OUT V = Max Outputs Open (I IN OUT VCC = Max MHz and I (or I and OZL IH OZH PALCE26V12H-15/20 (Com’l, Ind + +4. +5. – +5.5 V Min Max or V 2.4 IH ...
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... calculated value and is not guaranteed can be found using the following equation 1/f MAX (internal feedback) – Test Conditions + MHz OUT 1/( 1/( CNT S CF PALCE26V12H-15/20 (Com’l, Ind) AMD Typ Unit = 5 -15 -20 Min Max Min Max ...
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... T Clock t PD Registered V T Output 16072E-7 Input V T Output t WL 16072E-9 Input Asserting Synchronous V T Preset Clock ARR Registered V T Outputs 16072E-11 PALCE26V12 Family 16072E-8 Registered Output 0. 0.5V OL 16072E-10 ...
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... Don’t Care, Any Change Permitted Does Not Apply Output 300 5 pF PALCE26V12 Family OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL ...
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... AMD TYPICAL I CHARACTERISTICS FOR THE PALCE26V12H-7/ 5 150 125 100 75 ICC (mA The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching ...
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... ENDURANCE CHARACTERISTICS The PALCE26V12 is manufactured using AMD’s ad- vanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol Parameter t Min Pattern Data Retention Time DR N Min Reprogramming Cycles parts result, the device can be erased and reprogrammed— ...
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... AMD Bus-Friendly Inputs The PALCE26V12H-7/10 (Com’l) and H-10/15 (Ind) inputs and I/O loop back to the input after the second stage of the input buffer. This configuration reinforces INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION* ESD Protection * Device Rev. Letter PALCE26V12H-7 PALCE26V12H-10 C PALCE26V12H-15 2–322 the state of the input and pulls the voltage away from the input threshold voltage where noise can cause oscilla- tions ...
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... ROBUSTNESS FEATURES The PALCE26V12 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION* ESD Programming Protection Pins only and Clamping ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform PALCE26V12 Family can rise to its steady state, two CC rise must be monotonic. Max Unit 1000 ns See Switching Characteristics V ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. SKINNYDIP 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PALCE26V12H-15/20 AMD Typ PLCC Unit 19 18 ...
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... MAX ternal is measured. CLK LOGIC REGISTER External; 1/( MAX MAX PALCE26V12 Family internal”. A simple internal counter is a MAX .” CNT + t S type is the MAX + t ). Usually, this minimum feedback.” MAX no feedback are calculated pa- MAX external is calculated from t ...