PALCE26V12 AMD [Advanced Micro Devices], PALCE26V12 Datasheet - Page 21
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PALCE26V12
Manufacturer Part Number
PALCE26V12
Description
28-Pin EE CMOS Versatile PAL Device
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.PALCE26V12.pdf
(21 pages)
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f
The parameter f
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (t
ciprocal, f
feedback or in conjunction with an equivalent speed de-
vice. This f
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
2–326
MAX
AMD
Parameters
MAX
LOGIC
MAX
, is the maximum frequency with external
is designated “f
f
MAX
MAX
Internal (f
is the maximum clock rate at which
CNT
REGISTER
MAX
)
CLK
external.”
LOGIC
MAX
t
S
S
f
is specified for
MAX
+ t
CO
External; 1/(t
). The re-
PALCE26V12 Family
REGISTER
S
CLK
+ t
CO
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This f
designated “f
good example of this type of design, therefore, this pa-
rameter is sometimes called “f
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
ever, a lower limit for the period of each f
minimum clock period (t
clock period determines the period for the third f
designated “f
f
rameters. f
f
ternal is measured.
MAX
MAX
t
CO
)
no feedback is calculated from t
external and f
f
MAX
MAX
No Feedback; 1/(t
LOGIC
MAX
MAX
t
external is calculated from t
S
internal”. A simple internal counter is a
t
no feedback.”
S
(SECOND
MAX
CHIP)
no feedback are calculated pa-
WH
+ t
S
WL
+ t
CNT
REGISTER
). Usually, this minimum
H
.”
) or 1/(t
CLK
WL
and t
WH
MAX
S
S
and t
+ t
+ t
WH
type is the
WL
H
. f
16072E-18
). How-
CO
)
MAX
MAX
, and
MAX
in-
is
,