PIC18F25J11-I/PT MICROCHIP [Microchip Technology], PIC18F25J11-I/PT Datasheet - Page 225

• Manufacturer Part Number: PIC18F25J11-I/PT
• Description: 28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 16-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-2
bit 1-0
ALRMEN
R/W-0
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0000 0000
0 = Alarm is disabled
CHIME: Chime Enable bit
1 = Chime is enabled; ALRMRPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ALRMRPT<7:0> bits stop once they reach 00h
AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29
101x = Reserved – do not use
11xx = Reserved – do not use
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL
registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches
‘00’.
ALRMVALH<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVALL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
CHIME
R/W-0
and CHIME = 0)
ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F91h)
W = Writable bit
‘1’ = Bit is set
AMASK3
R/W-0
AMASK2
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
AMASK1
PIC18F46J11 FAMILY
R/W-0
AMASK0
R/W-0
th
, once every four years)
x = Bit is unknown
ALRMPTR1
R/W-0
DS39932C-page 225
ALRMPTR0
R/W-0
bit 0