FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 216
![no-image](/images/no-image-200.jpg)
FDC37B72X_07
Manufacturer Part Number
FDC37B72X_07
Description
128 Pin Enhanced Super I/O Controller with ACPI Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B72X_07.pdf
(238 pages)
- Current page: 216 of 238
- Download datasheet (832Kb)
NAME
t10
t11
t12
t13
t14
t15
t16
t1
t2
t3
t4
t5
t6
t7
t8
t9
nDACK Delay Time from FDRQ High
DRQ Reset Delay from nIOR or nIOW
FDRQ Reset Delay from nDACK Low
nDACK Width
nIOR Delay from FDRQ High
nIOW Delay from FDRQ High
Data Access Time from nIOR Low
Data Set Up Time to nIOW High
Data to Float Delay from nIOR High
Data Hold Time from nIOW High
nDACK Set Up to nIOW/nIOR Low
nDACK Hold after nIOW/nIOR High
TC Pulse Width
AEN Set Up to nIOR/nIOW
AEN Hold from nDACK
TC Active to PDRQ Inactive
TABLE 88 - BURST TRANSFER DMA TIMING
DESCRIPTION
217
MIN
150
40
10
10
10
60
40
10
0
0
0
5
TYP
MAX
100
100
100
100
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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