DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 109

• Manufacturer Part Number: DZPD6722VCCE
• Description: ISA-to-PC-Card (PCMCIA) Controllers
• Manufacturer: INTEL [Intel Corporation]

16.4.5
Datasheet
CLK
Symbol
V
V
V
T
T
V
IHCmin
ILCmax
Table 30. Input Clock Specification (Sheet 2 of 2)
Figure 22. Input Clock Specification
CLKP
CLKP
IHmin
ILmax
Input clock period,
internal clock
Input clock period,
external clock
CLK input high voltage
CLK input low voltage
CLK input high voltage
CLK input low voltage
PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by
first calculating factors derived from the applicable timer set’s timing registers and then by
applying the factor to an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as
follows:
t
1
Parameter
V
V
ILmax
IHmin
V
center
, V
, V
S = (N
C = (N
R = (N
IHCmin
ILCmax
pres
pres
pres
69.84 – 0.1%
40 – 0.1%
0.7 V
t
N
N
N
2
MIN
val
val
val
2.0
) + 1
) + 1
) + 1
DD
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
t
3
69.84 + 0.1%
40 + 0.1%
0.2 V
MAX
0.8
DD
T
CLKP
Units
ns
ns
V
V
V
V
t
4
Normal synthesizer
operation. Misc Control 2
register, bit 0 = ‘0’. CLK
pin at 14.318 MHz.
Synthesizer bypassed.
Misc Control 2 register,
bit 0 = ‘1’.
CLK pin at 25 MHz.
CORE_VDD = 3.0 V
CORE_VDD = 3.6 V
CORE_VDD = 4.5 V
CORE_VDD = 5.5 V
Conditions
109