DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 67

• Manufacturer Part Number: DZPD6722VCCE
• Description: ISA-to-PC-Card (PCMCIA) Controllers
• Manufacturer: INTEL [Intel Corporation]

9.4.0.1
9.5
Datasheet
Register Name: Card Memory Map 0–4 Offset Address Low
Index: 14h, 1Ch, 24h, 2Ch, 34h
Bit 7
Bits 3:0 — End Address 23:20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low register
(see
Bits 7:6 — Card Timer Select
This field selects the Timeset registers used to control socket timing for card accesses in this
window address range. Timeset 0 and 1 reset to values compatible with PC Card standards. The
mapping of bits 7:6 to Timeset 0 and 1, as shown in the preceding table, is done for software
compatibility with older ISA bus-based PC Card controllers that use ISA bus wait states instead of
Timeset registers (see
Card Memory Map 0–4 Offset Address Low
There are five separate Card Memory Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Bit 6
00
01
10
“System Memory Map 0–4 End Address Low” on page
11
23h
2Bh
33h
Index
14h
1Ch
24h
2Ch
34h
Selects Timer Set 0.
Selects Timer Set 1.
Selects Timer Set 1.
Selects Timer Set 1.
Bit 5
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
Card Memory Map Offset Address Low
Card Memory Map 0 Offset Address Low
Card Memory Map 1 Offset Address Low
Card Memory Map 2 Offset Address Low
Card Memory Map 3 Offset Address Low
Card Memory Map 4 Offset Address Low
“Setup Timing 0–1” on page
Offset Address 19:12
Bit 4
RW:00000000
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 3
84).
Bit 2
66).
Register Compatibility Type: 365
Bit 1
Register Per: socket
Bit 0
67