DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 110

• Manufacturer Part Number: DZPD6722VCCE
• Description: ISA-to-PC-Card (PCMCIA) Controllers
• Manufacturer: INTEL [Intel Corporation]

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
110
N
Command, and Recovery Timing registers (see
these registers).
From this, a PC Card cycle’s Setup, Command, and Recovery time for the selected timer set are
calculated as follows:
When the internal synthesizer is used, the calculation of the internal clock period Tcp is:
where T
14.318 MHz at the CLK input pin results in an internal clock period of Tcp = 40 ns.
When the internal synthesizer is bypassed, Tcp = T
circumstance would also result in an internal clock period of Tcp = 40 ns.
The timing diagrams that follow were derived for a PD67XX using the internal synthesizer and a
14.318-MHz CLK pin input. The internal clock frequency of the PD67XX is 7/4 of this incoming
signal (Tcp = 40 ns). The examples are for the default values of the Timing registers for Timer Set
0, as follows:
Thus the minimum times for the default values are as follows:
Default minimum Setup time = (S
Default minimum Command time = (C
Default minimum Recovery time = (R
Setup Timing 0
Command Timing 0
Recovery Timing 0
pres
Timing Register Name
and N
CLKP
(Timer Set 0)
val
is the period of the clock supplied to the CLK input pin. An input frequency of
are the specific selected prescaler and multiplier value from the timer set’s Setup,
Setup time = (S
Command time = (C
Recovery time = (R
Tcp = T
CLKP
Index
3Ch
4/7
3Ah
3Bh
Tcp) – 10 ns = {2
Tcp)
Tcp)
Tcp) – 10 ns = {4
Tcp)
Tcp) – 10 ns = {7 40 ns} – 10 ns = 270 ns
10 ns
(Default)
Value
“Timing Registers” on page 84
10 ns
01h
06h
03h
10 ns
CLKP
. An input frequency of 25 MHz in this
40 ns} – 10 ns = 70 ns
Resultant N
40 ns} – 10 ns = 150 ns
1
1
1
pres
Resultant N
for a description of
6
1
3
Datasheet
val