MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 166

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Input/Output (I/O) Ports
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
166
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTDPUE
Bit
X
1
0
Address:
DDRD
Reset:
Read:
Write:
Bit
0
0
1
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
DD
PTDPUE7
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
$000F
Bit 7
by internal pullup device.
0
PTDPUEx
PTD
X
Bit
X
X
(1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
PTDPUE6
6
0
Input, Hi-Z
Input, V
Table 13-5. Port D Pin Functions
RESET
Figure 13-15. Port D I/O Circuit
I/O Pin
Output
Mode
PTDPUE5
DD
VDD
(2)
(4)
5
0
INTERNAL
PULLUP
DEVICE
Table 13-5
PTDPUE4
Accesses to DDRD
DDRDx
PTDx
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
4
0
Read/Write
PTDPUE3
summarizes the operation of the port D pins.
3
0
PTDPUE2
2
0
PTD7–PTD0
Read
Pin
Pin
PTDPUE1
Accesses to PTD
1
0
Freescale Semiconductor
PTDPUE0
PTDx
Bit 0
0
PTD7–PTD0
PTD7–PTD0
PTD7–PTD0
Write
(3)
(3)