MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 226

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MC68HC908GZ8

Manufacturer Part Number
MC68HC908GZ8
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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System Integration Module (SIM)
Figure 16-16
16.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
226
and
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
CGMXCLK
R/W
Figure 16-17
IAB
IDB
Note:
RST
IDB
IAB
IDB
IAB
$A6
Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
WAIT ADDR
Figure 16-17. Wait Recovery from Internal Reset
$A6
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 16-16. Wait Recovery from Interrupt
$6E0B
$A6
show the timing for WAIT recovery.
PREVIOUS DATA
Figure 16-15. Wait Mode Entry Timing
$6E0B
$A6
$A6
WAIT ADDR + 1
$A6
CYCLES
$6E0C
32
NEXT OPCODE
$01
$00FF
CYCLES
32
$0B
SAME
$00FE
$6E
SAME
RST VCT H
$00FD
SAME
RST VCT L
$00FC
SAME
Freescale Semiconductor

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