MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 65

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 4-3
4.3.7 Special Programming Exceptions
The programming method described in
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
See
4.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
Freescale Semiconductor
11. Program the PLL registers accordingly:
•
•
4.3.8 Base Clock Selector
A 0 value for N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
provides numeric examples (register values are in hexadecimal notation):
(PMSH), program the binary equivalent of N. If using a 1–8 MHz reference, the PMSL register
must be reprogrammed from the reset value before enabling the pll.
1.25 MHz
2.0 MHz
2.5 MHz
3.0 MHz
4.0 MHz
5.0 MHz
7.0 MHz
8.0 MHz
500 kHz
f
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
BUS
Circuit.
Table 4-3. Numeric Example
4.3.6 Programming the PLL
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
f
RCLK
00C
01C
00A
002
005
008
010
014
020
N
does not account for two possible
E
0
0
0
1
1
1
2
2
2
1B
45
70
45
53
70
46
62
70
L
Functional Description
65