MC68HC908LJ12CPB FREESCALE [Freescale Semiconductor, Inc], MC68HC908LJ12CPB Datasheet - Page 377

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MC68HC908LJ12CPB

Manufacturer Part Number
MC68HC908LJ12CPB
Description
8-bit microcontroller units
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Low-Voltage Inhibit (LVI)
21.4 Functional Description
Technical Data
378
$FE0F
Addr.
Low-Voltage Inhibit Status
Register Name
Register
(LVISR)
Figure 21-2
The LVI is disabled out of reset. The LVI module contains a bandgap
reference circuit and comparator. Clearing the LVI power disable bit,
LVIPWRD, enables the LVI to monitor V
reset disable bit, LVIRSTD, enables the LVI module to generate a reset
when V
mode bit, LVISTOP, enables the LVI to operate in stop mode.
Reset:
Read: LVIOUT
Write:
Figure 21-1. LVI I/O Register Summary
FROM CONFIG2
DETECTOR
LVISEL[1:0]
LOW V
DD
Bit 7
V
DD
0
falls below a voltage, V
DD
shows the structure of the LVI module.
DEFAULT
DISABLED
Low-Voltage Inhibit (LVI)
Figure 21-2. LVI Module Block Diagram
= Unimplemented
LVIIE
TO LVISR
LVIOUT
6
0
FROM CONFIG1
LVIPWRD
V
V
DD
DD
LVIIF
> V
≤ V
5
0
TRIPR
TRIPF
DETECT
LATCH
EDGE
= 1
= 0
FROM LVISR
LVIIAK
LVIIACK
TRIPF
4
0
0
CLR
STOP INSTRUCTION
FROM CONFIG1
. Setting the LVI enable in stop
FROM LVISR
DD
LVIRSTD
TO LVISR
LVIIE
3
0
0
LVIIF
voltage. Clearing the LVI
MC68HC908LJ12
Freescale Semiconductor
0
0
2
FROM CONFIG1
LVISTOP
LVI RESET
LVI
INTERRUPT
REQUEST
1
0
0
Rev. 2.1
Bit 0
0
0

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