MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 143
MC68HC908QY2
Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908QY2.pdf
(230 pages)
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10.10.2 TIM Counter Registers
MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
NOTE:
PS[2:0] — Prescaler Select Bits
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as
PS[2:0] bits.
PS2
0
0
0
0
1
1
1
1
Timer Interface Module (TIM)
PS1
0
0
1
1
0
0
1
1
Table 10-2. Prescaler Selection
PS0
0
1
0
1
0
1
0
1
Table 10-2
shows. Reset clears the
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
TIM Clock Source
Not available
Timer Interface Module (TIM)
Input/Output Registers
143
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