MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 199
MC68HC908QY2
Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908QY2.pdf
(230 pages)
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16.5 LVI Status Register
MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
Address: $FE0C
The LVI status register (LVISR) indicates if the V
detected below the V
LVIOUT — LVI Output Bit
Reset:
Read: LVIOUT
Write:
This read-only flag becomes set when the V
V
V
that prevents oscillation into and out of reset (see
clears the LVIOUT bit.
TRIPF
TRIPR
Bit 7
. The difference in these threshold levels results in a hysteresis
0
trip voltage and is cleared when V
Figure 16-2. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
= Unimplemented
V
TRIPF
6
0
0
Table 16-1. LVIOUT Bit Indication
V
V
DD
DD
TRIPF
> V
V
V
DD
DD
V
TRIPR
TRIPF
5
0
0
level while LVI resets have been disabled
V
TRIPR
0
4
0
Previous value
R
3
0
0
LVIOUT
DD
DD
0
1
voltage rises above
= Reserved
DD
voltage falls below the
2
0
0
Low-Voltage Inhibit (LVI)
voltage was
Table
LVI Status Register
16-1). Reset
1
0
0
Bit 0
R
0
199
.
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