MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 81
MC68HC908QY2
Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908QY2.pdf
(230 pages)
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7.5.2 Active Resets from Internal Sources
MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
minimum of 67 BUSCLKX4 cycles, assuming that the POR was not the
source of the reset. See
relative timing.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see
Figure
opcode, COP time out, LVI, or POR (see
BUSCLKX4
ADDRESS BUS
ADDRESS
BUSCLKX2
IRST
RST
BUS
Reset Type
All others
RST
7-5). An internal reset can be caused by an illegal address, illegal
POR
System Integration Module (SIM)
PC
RST PULLED LOW BY MCU
Figure 7-4. External Reset Timing
Figure 7-5. Internal Reset Timing
Table 7-2. PIN Bit Set Timing
Table 7-2
32 CYCLES
Number of Cycles Required to Set PIN
for details.
4163 (4096 + 64 + 3)
67 (64 + 3)
Figure
System Integration Module (SIM)
32 CYCLES
Reset and System Initialization
VECT H VECT L
Figure 7-4
7-6).
VECTOR HIGH
shows the
81
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